1. Field of the Invention
The present invention relates to information handling systems and, more particularly, to control of access to data stored in memories in information handling systems.
2. Prior Art
Storage arrays in information handling systems are well-known in the art. As memory arrays get larger, it is beneficial to have data redundancy, word redundancy, and bit redundancy to increase effective yield and product reliability. In such large arrays, adding bit redundancy to word redundancy will generally result in increasing yield.
Adding redundancy at any level increases access time to reduce system performance. In general, word line redundancy is much simpler to implement and adds less access time to system performance than does bit line redundancy. Redundancy on larger memory elements is also possible.
Since redundancy adds to the delay of the array, the fastest, or peak, performance of the array is not attainable. However, the yield reliability of the memory is significantly increased. In a storage array having a large number of memory cells, even if memory has no defect, a performance penalty is still paid with prior art systems.
It is difficult to implement bit line redundancy when the data width of an array output in number of bits is large. For example, memory arrays may vary in the bit width of the outputs in the following increments: 1, 4, 8, 9, 16, 18, 32, and 36 bits wide. As the width of the memory output gets larger, it becomes increasingly difficult to multiplex the extra, or redundant, bits into any one of the outputs.
Another alternative is to have redundant bits associated uniquely with each output of the array such that if two redundant bits per output were added for a 36-bit-wide memory array, the area of the memory would increase by 1/n where n is the number of sets. Adding additional bits significantly increases the cost of the memory array.
In addition to the costs of adding area to an array, multiplexing adds additional time to memory access.
These problems are compounded for set associative cache arrays where multiple data are stored as different sets. For example, a four-way set associative cache accesses four separate data locations. It is not uncommon for set associative cache arrays to have wider outputs beyond 36 bits. Therefore, to add bit line redundancy to such set associative cache arrays would either add so much area to the array as to increase the cost beyond the benefit of increasing yield, or it would add additional access time which would effectively reduce performance of the system.
A system and method for allowing operation. of a storage array after a failure includes determining that there is a failure in the storage array, setting a flag to inhibit access to the portion of the array including the failure and storing and retrieving data from remaining portions of the array.
The present invention is well adapted for use with n-way set associative cache storage arrays.
It is an advantage of the present invention that a storage array such as a set associative cache array may be continued to be used for storage and retrieval of information, even in the event of a failure, by setting a flag to inhibit access to the portion of the array in which the failure occurred and allowing continued operation of the remaining, nonfailing portion of the array. Also, reliability is increased for the memory.